`timescale 1ns/1ps
`define data_0 10'b1110000000
`define data_1 10'b1111110000
module top_tb();
reg clk = 1'b0;
reg clkb = 1'b0;
reg [11:0] a = $random;
reg [11:0] b = $random;
reg [11:0] c = $random;
reg [9:0]  d = 111;//start_bit is 1,finish_bit is 0
reg [9:0]  d_bit;
reg e = 1'b0;
wire [11:0] y;
initial begin
	#(10+$random%5)
	repeat(10) begin
		d_bit <= (d[9]) ? `data_1 : `data_0;
		d <= d << 1; 
		repeat(10) @(posedge clkb)begin
			e <= d_bit[9];
			d_bit <= d_bit << 1;
		end
	end
end
always @(posedge clk) begin
	#0.1
	a = $random;
	b = $random;
	c = $random;
end
real result_real;
real real_a;
real real_b;
real real_c;
real real_d = real'(d);
always @(posedge clk)begin
	real_a <= real'(a);
	real_b <= real'(b);
	real_c <= real'(c);
	result_real <= #40 real_a*real_d/(real_a+real_b)*$sin(2*3.14159265358979323846*real_c/4096)*2;
end
wire [11:0] error = int'(result_real) - y;
always #2.5 clk <= ~clk;
always #1.5 clkb <= ~clkb;
top_predc u_top(
	.clk			(clk	),
	.a				(a		),
	.b				(b		),
	.c				(c		),
	.e 				(e 		),
	.y				(y      )
);
initial 
begin
    $fsdbDumpvars(0);
	// $fsdbDumpvars("+IO_Only");
end
initial 
begin
    $set_toggle_region(u_top);
	#1_000
	$toggle_start;
	#98_000
	$toggle_stop;
	$toggle_report("../Synthesize/results/backward_syn.saif",1.0e-12,"u_top");
end
initial 
begin
    $sdf_annotate("../Synthesize/results/top_predc.sdf",u_top);
end
endmodule